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Do you want to lift weights and watch some sparring? Hewlett-Packard purchased Compaq later that same year, continuing development of the existing product line until , and selling Alpha-based systems, largely to the existing customer base, until April A new Unix-like   operating system known as Mica would run applications natively, supporting VMS under emulation running at the same time.
However, development of the workstation was well ahead of the PRISM, and the engineers proposed that they release the machines using the MIPS R processor instead,  which would move its release date up by about a year.
Sun Microsystems was aggressively targeting former DEC Unix customers, providing machines with performance similar to DEC's highest-end units while costing a fraction of the price and fitting on a desktop.
After considerable study, they eventually concluded the only future path was an entirely new instruction set architecture based on pure RISC design.
When management accepted the findings, they decided to give the project a more neutral name, eventually settling on Alpha.
The primary Alpha instruction set architects were Richard L. Sites and Richard T. The main contribution of Alpha to the microprocessor industry, and the main reason for its performance, was not so much the architecture but rather its implementation.
The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the overly complex VAX architecture.
The Alpha chips showed that manual circuit design applied to a simpler, cleaner architecture allowed for much higher operating frequencies than those that were possible with the more automated design systems.
These chips caused a renaissance of custom circuit design within the microprocessor design community.
The first two digits, "21" signifies the 21st century, and the last two digits, "64" signifies 64 bits. The middle digit corresponded to the generation of the Alpha architecture.
The Alpha architecture was intended to be a high-performance design. Digital intended the architecture to support a one-thousandfold increase in performance over twenty-five years.
To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have:.
The Alpha does not have condition codes for integer instructions  to remove a potential bottleneck at the condition status register.
Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 64 bits, write the 32 or 64 least significant bits to the destination register.
The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand. If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition.
The architecture defined a set of 32 integer registers and a set of 32 floating-point registers in addition to a program counter , two lock registers and a floating-point control register FPCR.
It also defined registers that were optional, implemented only if the implementation required them. Lastly, registers for PALcode were defined.
The integer registers were denoted by R0 to R31 and floating-point registers were denoted by F0 to F The R31 and F31 registers were hardwired to zero and writes to those registers by instructions are ignored.
Digital considered using a combined register file, but a split register file was determined to be better as it enabled two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating point registers.
A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports.
The number of registers per register file was also considered, with 32 and 64 being contenders. Digital concluded that 32 registers was more suitable as it required less die space, which improved clock frequencies.
This number of registers was deemed not to be a major issue in respect to performance and future growth, as thirty-two registers could support at least eight-way instruction issue.
The program counter is a bit register which contains a longword-aligned virtual byte address, that is, the low two bits of the program counter are always zero.
The PC is incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support.
The floating-point control register FPCR is a bit register defined by the architecture intended for use by Alpha implementations with IEEE -compliant floating-point hardware.
In the Alpha architecture, a byte was defined as an 8-bit datum octet , a word as a bit datum, a longword as a bit datum, a quadword as a bit datum, and an octaword as a bit datum.
To maintain a level of compatibility with the VAX , the bit architecture that preceded the Alpha, two other floating-point data types were included:.
The Alpha has a bit linear virtual address space with no memory segmentation. Implementations can implement a smaller virtual address space with a minimum size of 43 bits.
Although the unused bits were not implemented in hardware such as TLBs , the architecture required implementations to check whether they are zero to ensure software compatibility with implementations with a larger or full virtual address space.
The integer operate format is used by integer instructions. It contains a 6-bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand.
Next is a 3-bit field which is unused and reserved. A 1-bit field contains a "0", which distinguished this format from the integer literal format.
A 7-bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to.
The register fields are all 5 bits long, required to address 32 unique locations, the 32 integer registers.
The integer literal format is used by integer instructions which use a literal as one of the operands. The format is the same as the integer operate format except for the replacement of the 5-bit Rb field and the 3 bits of unused space with an 8-bit literal field which is zero-extended to a bit operand.
The floating-point operate format is used by floating-point instructions. It is similar to the integer operate format, but has an bit function field made possible by using the literal and unused bits which are reserved in integer operate format.
The memory format is used mostly by load and store instructions. It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a bit displacement field.
Branch instructions have a 6-bit opcode field, a 5-bit Ra field and a bit displacement field. The Ra field specifies a register to be tested by a conditional branch instruction, and if the condition is met, the program counter is updated by adding the contents of the displacement field with the program counter.
The displacement field contains a signed integer and if the value of the integer is positive, if the branch is taken then the program counter is incremented.
If the value of the integer is negative, then program counter is decremented if the branch is taken. The Alpha Architecture was designed with a large range as part of the architecture's forward-looking goal.
The format retains the opcode field but replaces the others with a bit function field, which contains an integer specifying a PAL subroutine.
The control instructions consist of conditional and unconditional branches, and jumps. The conditional and unconditional branch instructions use the branch instruction format, while the jump instructions use the memory instruction format.
Conditional branches test whether the least significant bit of a register is set or clear, or compare a register as a signed quadword to zero, and branch if the specified condition is true.
The conditions available for comparing a register to zero are equality, inequality, less than, less than or equal to, greater than or equal to, and greater than.
The new address is computed by longword aligning and sign extending the bit displacement and adding it to the address of the instruction following the conditional branch.
Unconditional branches update the program counter with a new address computed in the same way as conditional branches.
They also save the address of the instruction following the unconditional branch to a register. There are two such instructions, and they differ only in the hints provided for the branch prediction hardware.
There are four jump instructions. These all perform the same operation, saving the address of the instruction following the jump, and providing the program counter with a new address from a register.
They differ in the hints provided to the branch prediction hardware. The unused displacement field is used for this purpose.
The integer arithmetic instructions perform addition, multiplication, and subtraction on longwords and quadwords; and comparison on quadwords.
There is no instruction s for division as the architects considered the implementation of division in hardware to be adverse to simplicity.
In addition to the standard add and subtract instructions, there are scaled versions. These versions shift the second operand to the left by two or three bits before adding or subtracting.
The Multiply Longword and Multiply Quadword instructions write the least significant 32 or 64 bits of a or bit result to the destination register, respectively.
UMULH is used for implementing multi-precision arithmetic and division algorithms. The concept of a separate instruction for multiplication that returns the most significant half of a result was taken from PRISM.
The instructions that operate on longwords ignore the most significant half of the register and the bit result is sign-extended before it is written to the destination register.
By default, the add, multiply, and subtract instructions, with the exception of UMULH and scaled versions of add and subtract, do not trap on overflow.
When such functionality is required, versions of these instructions that perform overflow detection and trap on overflow are provided. The compare instructions compare two registers or a register and a literal and write '1' to the destination register if the specified condition is true or '0' if not.
The conditions are equality, inequality, less than or equal to, and less than. With the exception of the instructions that specify the former two conditions, there are versions that perform signed and unsigned compares.
The logical instructions consist of those for performing bitwise logical operations and conditional moves on the integer registers.
The conditional move instructions test a register as a signed quadword to zero and move if the specified condition is true.
The specified conditions are equality, inequality, less than or equal to, less than, greater than or equal to, and greater than.
The shift instructions perform arithmetic right shift , and logical left and right shifts. The shift amount is given by a register or literal.
Logical and shift instructions use the integer operate instruction formats. Later, the Alpha included byte-word extensions, a set of instructions to manipulate 8-bit and bit data types.
These instructions were first introduced in the A EV56 microprocessor and are present in all subsequent implementations. These instructions performed operations that previously required multiple instructions to implement, which improved code density and the performance of certain applications.
BWX also made the emulation of x86 machine code and the writing of device drivers easier.